CCIE=0, IGNSF=0, FSFD=0, FDFD=0
Flash Configuration Register
FSFD | Force Single Bit Fault Detect 0 (0): Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected. 1 (1): Flash array read operation will force the SFDIF flag in the FERSTAT register to be set and an interrupt will be generated as long as FERCNFG[SFDIE] is set. |
FDFD | Force Double Bit Fault Detect 0 (0): Flash array read operations will set the FERSTAT[DFDIF] flag only if a double bit fault is detected. 1 (1): Any flash array read operation will force the FERSTAT[DFDIF] flag to be set and an interrupt will be generated as long as FERCNFG[DFDIE] is set. |
IGNSF | Ignore Single Bit Fault 0 (0): All single-bit faults detected during array reads are reported. 1 (1): Single-bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated. |
CCIE | Command Complete Interrupt Enable 0 (0): Command complete interrupt is disabled. 1 (1): An interrupt will be requested whenever the CCIF flag in the FSTAT register is set. |